Differential amplifier circuit with common mode output voltage regulation

ABSTRACT

The circuit comprises a differential amplifier ( 10 ) with two inputs and two outputs and a common mode regulation circuit. Between a regulation terminal (INCM) of the amplifier and the outputs there are connected a first (C 1   p ) and a second ( 1   m ) capacitor and first (C 3 ) and second (C 4 ) capacitive means that by means of controlled switches (SW 9 -SW 12 ) can be alternatively and simultaneousy connected in parallel with, respectively, the first ((C 1   p ) and the second (C 1   m ) capacitor or between a first (VB) and a second (Vref 1 ) reference voltage terminal. The capacitances C 3  and C 4  may be different in value such as to satisfy the following equality: Vcmn=Vref 1 +(Vrefp−Vrefm)/ 2 !*(C 4 −C 3 )/(C 3+ C 4 ), where Vcmn is the desired common mode output voltage, Vrefp and Vrefm are the differential output voltages and Vref 1  is the voltage of the second reference terminal are chosen in such a way as to satisfy the following equality: Vcmn=Vref 1+[ (Vrefp−Vrefm)/ 2 ]*(C 4− C 3 )/(C 3+ C 4 ), where Vcmn is the desired common mode output voltage, Vrefp and Vrefm are the differential output voltages and Vrefl is the voltage of the second reference terminal.

[0001] The present invention concerns switched capacitor circuits and,more particularly, a fully differential amplifier circuit with switchedcapacitors as defined in the preamble of claim 1.

[0002] As is well known, fully differential amplifiers are symmetricalcircuit structures with two inputs and two outputs that are used in manycircuit systems for processing analog and digital signals. They areused, for example, as operational amplifiers, comparators, impedanceseparator and adapter stages (buffers) and others. In operation thedifference between their output voltages is proportional to thedifference between the input voltages.

[0003] It is also known that if the output dynamics of the amplifier areto be optimized, the common mode output voltage, defined as thepotential (with respect to a given reference potential) of the centralpoint between the two output levels, must not differ very greatly from aconstant value chosen by the designer. With a view to obtaining thisresult, recourse is usually had to a feedback regulation by means of acircuit that senses the common mode output voltage and acts on anoperating parameter of the amplifier in such a way as to compensate anyphenomena tending to displace the common mode output voltage from thechosen value.

[0004] The technique based on the use of switched capacitors in place ofthe traditional resistors is used in many integrated circuits on accountof its advantages in terms of consumption, precision and space saving.

[0005] A known circuit employing a fully differential amplifier, acommon mode feedback circuit and switched capacitors for performing theintegrator function is described, for example, in an article entitled “Afamily of differential NMOS analog circuits for a PCM codec filterchip”, IEEE JSSC, December 1982, Page 1014.

[0006] A circuit similar to the one described in the above article canbe used as buffer for coupling a reference voltage generator, forexample, of the single-ended output type with one or more circuit stagesthat need a differential reference voltage. A known buffer of this type,which is schematically represented in FIG. 1, uses various capacitorswhose electrodes are selectively connected to various circuit nodes bymeans of two-way switches associated with the capacitors and controlledby a clock signal with two non-overlapping phases (generated by anappropriate circuit not shown in the figure). The positions of theswitches shown in the figure correspond to one of the two phases of theclock signal; in the other of the two phases all the switches are in theother position. A fully differential gain amplifier Av, indicated by thereference number 10, has an inverting input, a non-inverting input andtwo differential outputs Vrefp, Vrefm. Two capacitors CSp, CSm,so-called sampling capacitors, have respective electrodes that can beselectively connected by means of respective switches SW1, SW2 to theinverting input and the non-inverting input of the amplifier 10 or to aterminal of a biasing voltage generator indicated by Vcmi (common modeinput voltage). The other electrode of each of the two samplingcapacitors can be selectively connected by means of respective switchesSW3, SW4 to the single-ended output of a generator of a referencevoltage Vref referred to ground or to a common reference terminal of theintegrated circuit, here indicated by the ground symbol. It should benoted that when the capacitor CSp is connected to the terminal Vref, thecapacitor CSm is connected to ground, and vice versa. A capacitor CIp,the so-called integration capacitor, is connected between the invertinginput and the output Vrefp of the amplifier 10; another-capacitor CDp,the so-called dumping capacitor, can be connected in parallel with thecapacitor CIp by means of switches SW5 and SW6. The switches SW5 and SW6selectively connect the dumping capacitor CDp either in parallel withthe integration capacitor CIp or between the reference voltage terminalsVcmi and Vref. All integration capacitor CIm of the same capacity as thecapacitor CIp is connected between the non-inverting input and theoutput Vrefm of the amplifier 10, while a dumping capacitor CDm of thesame capacitance as the capacitor CDp can be selectively connected bymeans of switches SW7 and SW8 either in parallel with the capacitor CImor between the biasing voltage terminal Vcmi and the reference voltageterminal Vref.

[0007] The amplifier 10 has a common mode regulation terminal INCM thatmakes it possible to influence the functioning of the amplifier in sucha way as to cause the potentials of the differential output terminalsVrefp and Vrefm to vary in the same direction and therefore to displacethe common mode voltage with respect to ground potential. Two capacitorsC1 p and C1 m, which are of equal capacitance, are connected between theregulation terminal INCM and, respectively, the two amplifier outputsand can be respectively connected to one of two other capacitors C2 pand C2 m by means of switches SW9 and SW10, SW11 and SW12. Theseswitches can selectively connect the capacitors C2 p and C2 m alsobetween a biasing terminal VB and a reference terminal Vref1. The latterterminal is connected to the output of a level converter circuit 20 thathas its input connected to one terminal of a reference voltagegenerator, in this example to the reference voltage terminal Vref.

[0008] As will be clear to a person skilled in the art, when theswitches SW1-SW12 are operated in sequence by the clock signal, thecircuit that has just been described is a fully differential operationalamplifier and acts as a buffer between the reference voltage generatorVref and one or more user circuit stages connected to its outputs Vrefpand Vrefm. In particular, the differential output voltage isVrefp−Vrefm=2*CS/CD* Vref, where CS is the capacity of each of the twosampling capacitors CSp and CSm, and CD is the capacity of each of thetwo dumping capacitors CDp and CDm. It should be noted that thecapacitance of the integration capacitors determines only the timeconstant of the stabilization phase.

[0009] The circuit unit comprising the capacitors C1 p, C1 m and C1 p,C2 m constitutes a feedback circuit that, as already mentioned, has thetask of detecting the voltage levels of the amplifier outputs and tokeep them constant by acting on a common mode regulating parameter ofthe amplifier. In short, the unit has the function of maintaining thecommon mode output voltage constant at the predetermined value Vref.

[0010] Given the present trend of reducing the supply voltage ofintegrated circuits and the ever greater need for limiting both thepower consumption and the active area on the semiconductor in which theintegrated circuit is formed, the design of an operational differentialamplifier of the type just described becomes ever more difficult andcritical. In particular, the greatest difficulties derive from thedesire to have the highest possible differential voltage (for example:2V when the supply voltage is 2.5V), a high gain and a broad pass band.When the design constraints implied by these requirements becomesupplemented by the need for using an externally imposed voltage asreference voltage for the stabilization of the common mode outputvoltage, for example, to use an accurate and stabilized referencevoltage generator common to the entire integrated circuit, the design ofthe operational amplifier becomes even more difficult. Worse still, oncethe amplifier has been designed in an optimal manner to satisfy allthese requirements, a possible modification of the reference voltagewould call for an overhaul of the entire design. With a view to avoidingthis further difficulty, the operational amplifier is usually designedwithout defining a precise value of the reference voltage imposed fromoutside and shifting the common mode output level by means of a levelconverter that provides the common mode feedback circuit with a voltageof the right level to modify the common mode output voltage by theamount needed to obtain the desired value.

[0011] This expedient, in fact, renders the design of the buffer lessdifficult and critical, but involves a not by any means negligible wasteof integrated circuit area to accommodate the level converter. Theconverter, moreover, causes extra power consumption and noise.

[0012] The present invention therefore sets out to realize fullydifferential amplifier circuit of the type described above that willovercome the drawbacks associated with the state of the art, i.e. acircuit capable of exactly fixing the common mode output voltage thatcan be realized without occupying additional integrated circuit area or,at least, occupying only a minimal amount of additional area.

[0013] This aim is attained by the circuit defined and characterized ingeneral terms in claim 1 hereinbelow.

[0014] The invention will be understood more clearly from the detaileddescription about to be given of two embodiments thereof, which are tobe considered as examples and not limitative in any way, saiddescription making reference to the attached drawings of which:

[0015]FIG. 1 shows the schematic layout of a known differentialamplifier circuit with switched capacitors,

[0016]FIG. 2 shows the schematic layout of a differential amplifiercircuit with switched capacitors in accordance with a first embodimentof the invention, and

[0017]FIG. 3 shows the schematic layout of a differential amplifiercircuit with switched capacitors that constitutes a variant of thecircuit of FIG. 2.

[0018] It is important to precede the description of the invention withsome general considerations regarding the design of fully differentialamplifiers.

[0019] The typical advantages of differential circuits with respect tosingle-ended circuits are a small offset in direct current operation, agreater signal excursion, greater noise immunity and greater simplicityof design. A substantial part of these advantages is due to theconstructional symmetry of the two signal paths, usually referred to aspositive and negative. In this connection it should be borne in mindthat the advantages associated with the use of switched-capacitortechnique for the design of differential circuits include, among others,the greater accuracy with which capacitors can be realized in anintegrated circuit as compared with the traditional resistors, whichimplies a better approximation to the symmetry of the differentialcircuit. For these reasons, symmetry has become almost a dogma fordifferential circuit designers.

[0020] The present invention goes against this general trend, normallynot even called into question, and proposes the introduction of aconstructional asymmetry that makes it possible to simplify the designof a fully differential circuit and to obtain both a saving ofintegrated circuit area and a smaller power consumption of the circuitduring operation.

[0021] The schematic layout of the circuit in accordance with theinvention as shown in FIG. 2, where elements equal to those of FIG. 1are always identified by the same reference numbers, is very similar tothe known circuit of FIG. 1. Nevertheless, an important difference isrepresented by the absence of the level converter 20. Anotherdifference, not brought out by a simple examination of the circuitdiagramme, is the actual value of the two switched capacitances of thecommon mode feedback circuit, here indicated by C3 and C4. According tothe invention, these two capacitances are generally different from eachother. Thanks to their difference, the common mode output voltage, andtherefore the levels of the differential output voltages Vrefp andVrefm, are different from those that would be produced if the twocapacitances were identical. In particular, given an intervalVrefp-Vrefm and a reference voltage Vref1, which could be equal to thereference voltage Vref applied to the amplifier input, the capacitors C3and C4 can be chosen with capacitances such as to obtain a common modevoltage Vcmn that will generally be different from the applied referencevoltage Vref1. According to the invention, more precisely, thecapacitances of C3 and C4 must substantially satisfy the followingequality:

Vcmn=Vref1+[(Vrefp−Vrefm)/2]*(C4−C3)/(C3+C4)

[0022] In a practical application, with Vrefp−Vrefm=2V andVref1=Vref=1.35V, values of Vcmn comprised between 1,2V and 1.5V havebeen obtained by appropriately modifying the capacitances C3 and C4. Thesole negative effect deriving from this unbalancing that has been notedis that the feed-through of the feedback circuit has a differentialcontent that gives rise to offset. However, since the switches can bevery small and therefore also have very small intrinsic capacitances,the effect thus produced is negligible as compared with the offset ofthe amplifier circuit as a whole.

[0023] The invention may be advantageously put into practice also in thecase in which the reference voltage Vref1 is not exactly defined at thebeginning of the design of the differential amplifier circuit, forexample, because not all the components of the circuit system of whichit will eventually form part have yet been completely defined. In thiscase capacitive units of adjustable capacitance may be provided in placeof the capacitors C3 and C4. A practical example of this variant of theinvention is shown in FIG. 3. As can be seen, each unit comprises a“principal” capacitor, indicated by C3′ and C4′, and some “secondary”capacitors (three in this particular example, indicated by C3A, C3B,C3C; C4A, C4B and C4C) that may or may not be connected in parallel withtheir respective principal capacitor by means of, respectively, switchesSW3A, SW3B, SW3C; SW4A, SW4B, SW4C, respectively. These switches couldbe transistors controlled by fuses, a register, an EPROM or otherdevices, or could be formed by metallic connections capable of beingopened by one of the usual methods for calibrating integrated circuits.The use of transistors controlled by a register could be the mostconvenient solution, because it makes it possible for the capacitiveunits to be easily regulated also in the phase of adjusting and testingthe circuit system that contains the amplifier in accordance with theinvention.

[0024] In a practical application of the invention in which Vref=1.35V,(Vrefp−Vrefm)=2V, C3′=C4′=450 fF, C3A=C3B=C3C=C4A=C4B=C4C=50fF, a commonmode voltage Vcmn=1.25V can be obtained by connecting only thecapacitors C3A and C3B in parallel with the capacitor C3′, so thatC3′=550fF e C4′=450fF.

[0025] It is clear from what has been said above that the aim of theinvention is fully attained thanks to the fact that the common modeoutput voltage can be set with precision by merely regulating thecapacitance of the two capacitors and without employing any additionalcircuit area.

1. A fully differential amplifier circuit with switched capacitorscomprising a differential amplifier (10) having a first and a secondinput terminal, a first and a second output terminal (Vrefp, Vrefm) anda common mode regulation terminal (INCM), a common mode regulationcircuit comprising a first (C1 p) and a second (C1 m) capacitorconnected between the common mode regulation terminal (INCM) and,respectively, the first (Vrefp) and the second (Vrefm) output terminaland first (C3) and second (C4) capacitive means with associatedcontrolled switching means (SW9-SW12) capable of alternatively andsimultaneously connecting the first (C3) and the second (C4) capacitivemeans in parallel with, respectively, the first (C1 p) and the second(C1 n) capacitor or between a biasing voltage terminal (VB) and areference voltage terminal (Vref1), characterized in that the first (C3)and the second (C4) capacitive means are chosen with capacitances suchthat the common mode output voltage will substantially satisfy thefollowing equality: Vcmn=Vref1+[(Vrefp−Vrefm)/2]*(C4−C3)/(C3+C4) whereVcmn is the desired common mode voltage, Vref1 is the voltage at thereference voltage terminal (Vref1), Vrefp and Vrefm are the voltages at,respectively, the first (Vrefp) and the second (Vrefm) output terminal,and C3 and C4 are the capacitances of, respectively, the first (C3) andthe second (C4) capacitive means.
 2. A circuit in accordance with claim1, wherein the first and the second capacitive means comprise capacitiveunits (C3′, C3A, C3B, C3C; C4′, C4A, C4B, C4C) of adjustablecapacitance.
 3. A circuit in accordance with claim 2, wherein each ofthe capacitive units comprises a multiplicity of capacitors andassociated selectively controllable connecting elements (SW3A, SW3B,SW3C; SW4A, SW4B, SW4C) to regulate the capacitance of the capacitiveunits.
 4. A circuit in accordance with any one of the preceding claimscomprising two sampling capacitors (CSp, CSm) having respective firstelectrodes that can be selectively connected by means of respectivecontrolled switches (SW1, SW2) to the first and the second inputterminal of the amplifier (10) and respective second electrodes that canbe selectively connected by means of respective controlled switches(SW3, SW4) to the output of a reference voltage generator (Vref) or to acommon reference terminal.
 5. A circuit in accordance with any one ofthe preceding claims comprising, respectively between the first inputterminal and the first output terminal and between the second inputterminal and the second output terminal, a first (CIp) and a second(CIm) integration capacitor and a first and a second dumping capacitor(CDp, CDm) that can be connected in parallel with the first and secondintegration capacitor by means of respective controlled switches (SW5,SW6).
 6. A circuit system comprising an amplifier circuit in accordancewith any one of the preceding claims, a generator of a single-endedreference voltage and coupling means between the output of the referencevoltage generator and each of the input terminals of the differentialamplifier, wherein the reference voltage terminal is connected to theoutput of the reference voltage generator.